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HV9708 HV9808 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs
Ordering Information
Package Options Device 44 J-Lead Quad Plastic Chip Carrier HV9708PJ HV9808PJ Die in waffle pack HV9708X HV9808X
HV9708 HV9808
Features
Processed with HVCMOS(R) technology Output voltages up to 80V Low power level shifting Shift register speed 8MHz Latched data outputs Forward and reverse shifting options Diode to VPP allows efficient power recovery 5V CMOS compatible inputs
General Description
The HV97 and HV98 are low-voltage serial to high-voltage parallel converters with push-pull outputs. These devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The inputs are fully CMOS compatible. These devices consist of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the shift register through the polarity and blanking logic. Data is shifted through the shift register on the logic low to high transition of the clock. The HV97 shifts data in the clockwise direction when viewed from the top of the package and the HV98 shifts in the counterclockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT32). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low.
Absolute Maximum Ratings1
Supply voltage, VDD2 Output voltage, VPP2 Logic input levels2 Ground current3 Continuous total power dissipation4 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds -0.5V to +7V VDD to +90V -0.5V to VDD +0.5V 1.5A 1200mW -40C to +85C -65C to +150C 260C
Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to GND. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25C ambient, derate linearly to 70C at 12mW/C. 02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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HV9708/HV9808
Electrical Characteristics (VPP = 60V, VDD = 5V, TA =25C)
DC Characteristics
Symbol IPP IDDQ IDD VOH (Data) VOL (Data) IIH IIL VOC VOH VOL Parameter VPP Supply Current IDD Supply Current (Quiescent) IDD Supply Current (Operating) Shift Register Output Voltage Shift Register Output Voltage Current Leakage, any input Current Leakage, any input HVOUT Output Clamp Diode Voltage HVOUT Output when Sourcing HVOUT Output when Sinking 52 4 VDD-0.5 0.5 1 -1 -1.5 Min Max 100 100 15 Units A A mA V V A A V V V Conditions HVOUT outputs HIGH to LOW All inputs = VDD or GND VDD = VDD max, fCLK = 8 MHz IO = -100A IO = 100A Input = VDD Input = GND IOC = -5mA IOH = -20mA, 0 to 70C IOL = 5mA, 0 to 70C
AC Characteristics
Symbol fCLK tWL or tWH tSU tH tDLH (Data) tDHL (Data) tDLE tWLE tSLE tON tOFF Parameter Clock Frequency Clock width, HIGH or LOW Setup time before CLK rises Hold time after CLK rises Data Output Delay after L to H CLK Data Output Delay after H to L CLK LE Delay after L to H CLK Width of LE Pulse LE Setup Time before L to H CLK Delay from LE to HVOUT, L to H Delay from LE to HVOUT, H to L 50 50 50 500 500 62 25 10 110 110 Min Max 8 Units MHz ns ns ns ns ns ns ns ns ns ns CL = 15pF CL = 15pF Conditions
Recommended Operating Conditions
Symbol VDD VPP VIH VIL fCLK TA Parameter Logic Voltage Supply High Voltage Supply Input HIGH Voltage Input LOW Voltage Clock Frequency Operating free-air temperature Min 4.5 8.0 VDD-0.5 0 0 -40 Max 5.5 80 VDD 0.5 8 +85 Units V V V V MHz C Comments
Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. 5. The VPP should not drop below VDD or float during operations.
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HV9708/HV9808
Input and Output Equivalent Circuits
VDD VDD VPP
Input
Data Out
HVOUT
GND Logic Inputs
GND Logic Data Output
GND High Voltage Outputs
Switching Waveforms
VIH Data Input 50% tSU Clock 50% tWL 50% tWH 50% VOL Data Out tDLH 50% tDHL VOH VOL Data Valid tH VIH 50% 50% VIL VOH 50% VIL
Latch Enable tDLE
50% tWLE
50% tSLE
VIH VOL
HVOUT w/ S/R LOW tOFF HVOUT w/ S/R HIGH
90% 10%
VOH VOL
10% tON
90%
VOH VOL
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HV9708/HV9808
Functional Block Diagram
VPP Polarity Blanking Latch Enable
Data Input Clock
HVOUT1 Latch HVOUT2
Latch 32-Bit Shift Register
(Outputs 3 to 30 not shown) HVOUT31
Latch
Data Out
Latch
HVOUT32
Function Table
Inputs Function All on All off Invert mode Load S/R Load latches Transparent latch mode Data X X X H or L X X L H CLK X X X
Outputs BL L L H H H H H H POL L H L H H L H H Shift Reg 1 2...32 * * * *...* *...* *...* HV Outputs 1 2...32 H L * * * * L H H...H L...L *...* *...* *...* *...* *...* *...* Data Out * * * * * * * * *
LE X X L L

H or L *...* * * L H *...* *...* *...* *...*
H or L H or L

H H
Notes: H = high level, L = low level, X = irrelevant, = low-to-high transition. * = dependent on previous stage's state before the last CLK or last LE high.
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HV9708/HV9808
Pin Configurations
HV97 44 Pin J-Lead Package
Package Outline
39 38 37 36 35 34 33 32 31 30 29
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Function HVOUT 17 HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Data Out NC NC Polarity Clock
Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Function GND VPP VDD Latch Enable Data In Blanking NC HVout 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 HVOUT 23 HVOUT 22 HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18
40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
28 27 26 25 24 23 22 21 20 19 18
top view 44-pin J-Lead Package
HV98 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 Data Out NC NC Polarity Clock Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function GND VPP VDD Latch Enable Data In Blanking NC HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10 HVOUT 11 HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15
02/06//02
(c)2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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